File:NMI timing diagram.svg
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NMI_timing_diagram.svg (SVG file, nominally 678 × 951 pixels, file size: 42 KB)
Diagram of worst case timings of interrupt service routines for quad density floppy disc access. According to Sonninen et al. in 64doc, to interrupt the next instruction the NMI must arrive before the last cycle of the current instruction. Thus, in the worst case, the first NMI arrives just less than one cycle before the start of an instruction (this interval is shown by a white rectangle), and an instruction starting at 15 µs is allowed to continue.
If 64doc is incorrect then the timings still hold true; all the instruction rectangles just move 1 clock cycle to the left such that each ISR gets 0.5 µs more time to service the floppy drive controller.
My own work. – beardo 13:44, 20 September 2010 (UTC)
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(Latest | Earliest) View (newer 50) (older 50) (20 | 50 | 100 | 250 | 500)| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 13:32, 20 September 2010 | | 678×951 (42 KB) | Beardo (Talk | contribs) | (Removed the EDOSpat 5.01 Tube write and added the successful 2 MHz I/O reads.) |
| 16:13, 13 August 2009 |  | 678×951 (37 KB) | Beardo (Talk | contribs) | (STA abs,X always takes 5 memory cycles – reading from disc to 1 MHz I/O memory stores to the wrong page in some circumstances and may overflow the stack. :( ~~~~) | |
| 00:51, 29 July 2009 |  | 673×951 (38 KB) | Beardo (Talk | contribs) | (Diagram of worst case timings of interrupt service routines for quad density floppy disc access. According to Sonninen et al. in [http://www.nvg.org/bbc/doc/6502.txt 64doc], to interrupt the next instruction the NMI must arrive before the last cycle ) |
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