File:Nmi rdio 16us check.svg
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Nmi_rdio_16us_check.svg (SVG file, nominally 682 × 530 pixels, file size: 35 KB)
Extended timing diagrams for the worst case of reading to I/O memory. NMIs must be no less than 16 − ε µs apart. The ε (epsilon) means that in the worst case the NMIs will just miss one decision point and just catch the next.
There are two CPU timing diagrams wrapped over four rows each. In the top diagram the first STA instruction is out of phase with the 1MHzE clock shown underneath and must take 1 cycle longer; in the bottom diagram it is in phase. In either case the CPU soon settles into sync with the NMIs. If the floppy drive controller itself is on the 1 MHz bus and does not need EOR #&FF instructions, the timing is no worse than shown.
CPU activities are colour coded into grey: fixed task; yellow: FDC not serviced; pink: NMI routine not re-entrant; blue: working set on stack. For more details see File:NMI timing diagram.svg and Quad density floppy disc access.
My own work. – beardo 16:43, 1 November 2009 (UTC)
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(Latest | Earliest) View (newer 50) (older 50) (20 | 50 | 100 | 250 | 500)| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 16:02, 1 November 2009 | | 682×530 (35 KB) | Beardo (Talk | contribs) | (upload correct version) |
| 15:55, 1 November 2009 |  | 639×487 (28 KB) | Beardo (Talk | contribs) | (Diagram confirming that the ISR to read from disc into I/O memory behaves correctly with a worst case sequence of NMIs no less than 16 − ε µs apart. The ε (epsilon) means that in the worst case the NMIs will just miss one decision point and just cat) |
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